Field of the Invention
Memory cell configurations, in particular DRAM configurations, ROM configurations, EPROM configurations and EEPROM configurations, have a multiplicity of memory cells that are usually disposed in the form of a matrix. In this case, the individual memory cells can each be driven via a bit line and a word line. The memory cells each have a storage element in which information is stored. The information is stored, for example, by a charge stored in a storage capacitance, by a charge stored on a floating gate, or by properties of a transistor, for example the threshold voltage, or by the presence or absence of a conductive connection to the bit line.
In order to read out the information, the individual memory cells are driven sequentially via the associated word line and bit line and the information is read out by voltage or current evaluation (see, for example, Y. Nakagome et al., IEEE Journal of Solid-State Circuits, Vol. 26, No. 4, 1991, pages 465 to 470). With regard to the reading speed, current evaluation is preferable to voltage evaluation but it requires an increased outlay in terms of circuitry. In order to accelerate the reading operation, it is frequently the case that a plurality of memory cells, for example 256, are combined to form a cell block. The individual cell blocks are then read out in parallel. However, the read-out operation in the individual cell block is still carried out sequentially.
In electrically writable memory cell configurations, for example DRAM configurations or EEPROM configurations, in order to write in information, the respective memory cell is likewise driven via the associated bit line and the word line. At the same time, a voltage level corresponding to the information to be written in is applied to the bit line. The information is written sequentially to all the memory cells. In this case, the bit line must each time undergo charge reversal from one voltage state to the other voltage state. This is associated with a consumption of electrical power which is found to be disturbing particularly when the memory cell configuration is used in mobile equipment such as, for example, mobile telephones, notebook computers, database computers or PDA (personal digital assistant).
In DRAM configurations, moreover, the problem arises that the stored information must be refreshed again at regular time intervals. For this purpose, the information is initially read sequentially from the memory cells and then written back. An undesirable power consumption occurs in this case, too.
A further problem in the context of DRAM configurations is the storage density, which increases from memory generation to memory generation. Associated with this is the requirement for an increased packing density, that is to say a reduction in the space requirement per memory cell. German Patent DE 19 519 160 C1 discloses a DRAM cell configuration which can be fabricated with a memory cell area of 4F.sup.2, where F is the minimum structure size that can be fabricated using the respective technology. In this case, a vertical MOS transistor is provided for each memory cell, the first source/drain region of the transistor is connected to a storage node of a storage capacitor. A channel region of the transistor is enclosed annularly by a gate electrode, and the second source/drain region of the transistor is connected to a buried bit line. The gate electrodes of neighboring vertical MOS transistors along a word line adjoin one another and jointly form the word line.